Latch-Up Effect

Under normal operating conditions, the device automatically switches off and reverts to a high-impedance state once the current through the device falls below the holding current ISB. However, latch-up will occur if the supply voltage of the circuit system exceeds the holding voltage and the on-state current remains higher than ISB. Even after the external ESD event disappears, the device cannot turn off and stays in a low-impedance, high-current conducting state. This causes voltage drop on protected downstream circuits, potentially resulting in system malfunction. Furthermore, sustained high current through the ESD protection device may lead to permanent damage. Therefore, during device selection, engineers should prioritize ESD protection devices with holding voltage higher than the system normal operating voltage. In areas highly susceptible to latch-up, devices with strong Snap-Back characteristics should be avoided to mitigate latch-up risks.

Chip Structure of Snap-Back Devices – SCR

What Is the SCR Structure?

As circuits grow increasingly sensitive to parasitic effects, the drawbacks of traditional GGNMOS structures become more prominent. SCR (Silicon-Controlled Rectifier) has emerged as a promising ESD protection device. The SCR structure forms a four-layer PNPN stack consisting of parasitic diodes, an N-well and P-substrate, creating a parasitic silicon-controlled rectifier. When the ESD voltage exceeds the trigger threshold, the internal positive feedback loop (simultaneous turn-on of parasitic NPN and PNP transistors) activates, switching the device rapidly into a low-impedance conducting state to divert ESD current. The chip structure and equivalent circuit of our low-capacitance bidirectional SCR-based ESD diode are shown below. Compared with conventional PN-junction ESD diodes, it achieves lower clamping voltage and smaller junction capacitance.